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1 white electronic designs corporation ?(508) 366-5151 ?www.whiteedc.com wed9lc6416v january 20001 description the wed9lc6416vxxbc is a 3.3v, 128k x 32 synchronous pipeline sram and a 4mx32 synchronous dram array con- structed with one 128k x 32 sbsram and two 4mx16 sdram die mounted on a multilayer laminate substrate. the device is packaged in a 153 lead, 14mm by 22mm, bga. the wed9lc6416vxxbc provides a total memory solution for the texas instruments tms320c6201 and the tms320c6701 dsps the synchronous pipeline sram is available with clock speeds of 200, 166,150, and 133 mhz, allowing the user to develop a fast external memory for the ssram interface port . the sdram is available in clock speeds of 125 and 100 mhz, allowing the user to develop a fast external memory for the sdram interface port . the wed9lc6416v is available in both commercial and industrial temperature ranges. 128kx32 ssram/4mx32 sdram external memory solution for texas instruments tms320c6000 dsp features clock speeds: ? ssram: 200, 166,150, and 133 mhz ? sdrams: 125 and 100 mhz dsp memory solution ? texas instruments tms320c6201 ? texas instruments tms320c6701 packaging: ? 153 pin bga, jedec mo-163 3.3v operating supply voltage direct control interface to both the ssram and sdram ports on the c6x common address and databus 65% space savings vs. monolithic solution reduced system inductance and capacitance fig. 1 pin configuration 12 3456 789 a dq 19 dq 23 v cc v ss v ss v ss v cc dq 24 dq 28 a b dq 18 dq 22 v cc v ss sdce v ss v cc dq 25 dq 29 b c v ccq v ccq v cc sdwe sda 10 nc v cc v ccq v ccq c d dq 17 dq 21 v cc v ss v ss v ss v cc dq 26 dq 30 d e dq 16 dq 20 v cc v ss sdclk v ss v cc dq 27 dq 31 e f v ccq v ccq v cc v ss v ss v ss v cc v ccq v ccq f g nc nc nc sdras sdcas v ss a 2 a 4 a 5 g h nc nc a 8 v ss v ss nc a 1 a 3 a 10 h j a 6 a 7 a 9 v ss v ss nc a 0 a 11 a 12 j k nc / a 17 nc / a 18 nc / a 19 v ss v ss nc nc a 13 a 14 k l nc nc nc bwe 2 bwe 3 nc nc a 15 a 16 l m v ccq v ccq v cc bwe 0 bwe 1 nc v cc v ccq v ccq m n dq 12 dq 11 v cc v ss v ss v ss v cc dq 4 dq 0 n p dq 13 dq 10 v cc v ss ssclk v ss v cc dq 5 dq 1 p r v ccq v ccq v cc v ss v ss v ss v cc v ccq v ccq r t dq 14 dq 9 v cc ssadc sswe nc v cc dq 6 dq 2 t u dq 15 dq 8 v cc ssoe ssce nc v cc dq 7 dq 3 u 12 3456 789 top view a 0-16 address bus dq 0-31 data bus ssclk ssram clock ssadc ssram address status control sswe ssram write enable ssoe ssram output enable sdclk sdram clock sdras sdram row address strobe sdcas sdram column address strobe sdwe sdram write enable sda 10 sdram address 10/auto precharge bwe 0-3 ssram byte write enables sdram sdqm 0 - 3 ssce chip enable ssram device sdce chip enable sdram device v cc power supply pins, 3.3v v ccq data bus power supply pins, 3.3v (2.5v future) v ss ground nc no connect pin description advanced* * this data sheet describes a product that may or may not be under development and is subject to change or cancellation without notice.
2 white electronic designs corporation ?(508) 366-5151 ?www.whiteedc.com wed9lc6416v january 2001 fig. 2 block diagram a 0 a 1 a 2 a 3 a 4 a 5 a 6 a 7 a 8 a 9 a 11 a 10 /ap ldqm udqm cs ras cas we clk dq 0-7 dq 8-15 a 0 a 1 a 2 a 3 a 4 a 5 a 6 a 7 a 8 a 9 a 10 a 11 a 12 a 13 a 14 a 15 a 16 bwe bw 1 bw 2 bw 3 bw 4 ce 2 oe adsc clk dq 1-8 dq 9-16 dq 17-24 dq 25-32 a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a 11 a 10 /ap ldqm udqm cs ras cas we clk dq 0-7 dq 8-15 dq 0-31 a 0-16 a 0 a 1 sswe bwe 0 bwe 1 bwe 2 bwe 3 ssce ssoe ssadc ssclk sda 10 sdce sdras sdcas sdwe sdclk dq 0-7 dq 8-15 dq 16-23 dq 24-31 dq 0-7 dq 8-15 dq 16-23 dq 24-31 ba 0 ba 1 a 13 a 12 a 13 a 12 ba 0 ba 1
3 white electronic designs corporation ?(508) 366-5151 ?www.whiteedc.com wed9lc6416v january 20001 output functional descriptions symbol type si gnal polarity function ssclk input pulse positive edge the system clock input. all of the ssram inputs are sampled on the rising edge of the clock. ssads when sampled at the positive rising edge of the clock, ssads, ssoe, and sswe define the operation ssoe input pulse active low to be executed by the ssram. sswe ssce input pulse active low ssce disable or enable ssram device operation. sdclk input pulse positive edge the system clock input. all of the sdram inputs are sampled on the rising edge of the clock. sdce input pulse active low sdce disable or enable device operation by masking or enabling all inputs except sdclk and bwe 0-3 . sdras when sampled at the positive rising edge of the clock, sdcas, sdras, and sdwe define the operation sdcas input pulse active low to be executed by the sdram. sdwe address bus for ssram and sdram a 0 and a 1 are the burst address inputs for the ssram during a bank active command cycle, a 0-11 , sda 10 defines the row address (ra 0-10 ) when sampled at the rising clock edge. a 0-16 , input level during a read or write command cycle, a 0-7 defines the column address (ca 0-7 ) when sampled at the sda 10 rising clock edge. in addition to the row address, sda 10 is used to invoke autoprecharge operation at the end of the burst read or write cycle. if sda 10 is high, autoprecharge is selected and a 12 and a 13 define the bank to be precharged. if sda 10 is low, autoprecharge is disabled. during a precharge command cycle, sda 10 is used in conjunction with a 12 and a 13 to control which bank(s) to precharge. if sda 10 is high, all banks will be precharged regardless of the state of a 12 and a 13 . if sda 10 is low, then a 12 and a 13 are used to define which bank to precharge. dq 0-31 input level data input/output are multiplexed on the same pins. output bwe 0-3 input pulse bwe 0-3 perform the byte write enable function for the ssram and dqm function for the sdram. bwe 0 is associated with dq 0-7 , bwe 1 with dq 8-15 , bwe 2 with dq 16-23 and bwe 3 with dq 24-31 . vcc, vss supply power and ground for the input buffers and the core logic. v ccq supply data base power supply pins, 3.3v (2.5v future).
4 white electronic designs corporation ?(508) 366-5151 ?www.whiteedc.com wed9lc6416v january 2001 recommended dc operating conditions (v cc = 3.3v -5% / +10% unless otherwise noted; 0 c t a 70 c, commercial; -40 c t a 85 c, industrial) absolute maximum ratings *stress greater than those listed under "absolute maximum ratings" may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions greater than those indicated in operational sections of this specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. voltage on vcc relative to vss -0.5v to +4.6v vin (dqx) -0.5v to vcc +0.5v storage temperature (bga) -55 c to +125 c junction temperature +175 c short circuit output current 100 ma parameter symbol min max units supply voltage (1) v cc 3.135 3.6 v input high voltage (1,2) v ih 2.0 v cc +0.3 v input low voltage (1,2) v il -0.3 0.8 v input leakage current il i -10 10 a 0 v in vcc output leakage (output disabled) ilo -10 10 a 0 v in vcc output high (i oh = -4ma) (1) v oh 2.4 v output low (i ol = 8ma) (1) v ol 0.4 v notes: 1. all voltages referenced to vss (gnd). 2. overshoot: v ih +6.0v for t t kc /2 underershoot: v il -2.0v for t t kc /2 dc electrical characteristics (v cc = 3.3v -5% / +10% unless otherwise noted; 0 c t a 70 c, commercial; -40 c t a 85 c, industrial) description conditions symbol frequency typ max units power supply current: 133mhz 400 550 operating (1,2,3) ssram active / dram auto refresh icc 1 150mhz 450 580 ma 166mhz 500 625 200mhz 550 700 power supply current 133mhz 300 450 operating (1,2,3) ssram active / dram idle icc 2 150mhz 350 480 ma 166mhz 400 525 200mhz 450 585 power supply current 83mhz 220 240 operating (1,2,3) sdram active / ssram idle icc 3 100mhz 235 250 ma 125mhz 255 280 ssce and sdce vcc -0.2v, i sb1 20.0 40.0 cmos standby all other inputs at vss +0.2 v in or ma v in v cc -0.2v, clk frequency = 0 ssce and sdce v ih min i sb2 30.0 55.0 ttl standby all other inputs at v il max v in or ma v in v cc -0.2v, clk frequency = 0 auto refresh icc 5 190 250 ma notes: 1. i cc (operating) is specified with no output current. i cc (operating) increases with faster cycle times and greater output loading. 2. "device idle" means device is deselected (ce v ih ) clock is running at max frequency and addresses are switching each cycle. 3. typical values are measured at 3.3v, 25 c. i cc (operating) is specified at specified frequency. description conditions symbol typ max units address input capacitance (1) t a = 25 c; f = 1mhz c i 58pf input/output capacitance (dq) (1) t a = 25 c; f = 1mhz c o 810pf control input capacitance (1) t a = 25 c; f = 1mhz c a 58pf clock input capacitance (1) t a = 25 c; f = 1mhz c ck 46pf note: 1. this parameter is sampled. bga capacitance
5 white electronic designs corporation ?(508) 366-5151 ?www.whiteedc.com wed9lc6416v january 20001 ssram ac characteristics (v cc = 3.3v -5% / +10% unless otherwise noted; 0 c t a 70 c, commercial; -40 c t a 85 c, industrial) symbol 200mhz 166mhz 150mhz 133mhz parameter min max min max min max min max units clock cycle time t khkh 5678ns clock high time t klkh 1.6 2.4 2.6 2.8 ns clock low time t khkl 1.6 2.4 2.6 2.8 ns clock to output valid t khqv 2.5 3.5 3.8 4.0 ns clock to output invalid t khqx 1.5 1.5 1.5 1.5 ns clock to output on low-z t kqlz 0000ns clock to output in high-z t kqhz 1.5 3 1.5 3.5 1.5 3.8 1.5 4.0 ns output enable to output valid t oelqv 2.5 3.5 3.8 4.0 ns output enable to output in low-z t oelz 0000ns output enable to output in high-z t oehz 3.0 3.5 3.5 3.8 ns address, control, data-in setup time to clock t s 1.5 1.5 1.5 1.5 ns address, control, data-in hold time to clock t h 0.5 0.5 0.5 0.5 ns
6 white electronic designs corporation ?(508) 366-5151 ?www.whiteedc.com wed9lc6416v january 2001 operation address used ssce ssads sswe ssoe dq deselected cycle, power down none h l x x high-z write cycle, begin burst external l l l x d read cycle, begin burst external l l h l q read cycle, begin burst external l l h h high-z read cycle, suspend burst current x h h l q read cycle, suspend burst current x h h h high-z read cycle, suspend burst current h h h l q read cycle, suspend burst current h h h h high-z write cycle, suspend burst current x h l x d write cycle, suspend burst current h h l x d note: 1. x means ?on? care? h means logic high. l means logic low. 2. all inputs except ssoe must meet setup and hold times around the rising edge (low to high) of ssclk. 3. suspending burst generates wait cycle 4. for a write operation following a read operation, ssoe must be high before the input data required setup time plus high-z tim e for ssoe and staying high though out the input data hold time. 5. this device contains circuitry that will ensure the outputs will be in high-z during power-up. ssram operation truth table ssram partial truth table function sswe bwe 0 bwe 1 bwe 2 bwe 3 read h x x x x write one byte (dq0-7) l l h h h write all bytes l l l l l
7 white electronic designs corporation ?(508) 366-5151 ?www.whiteedc.com wed9lc6416v january 20001 fig. 3 ssram read timing t h t khqx t kqlz q(a1) q(a2) q(a3) q(a4) t khqv q(a5) a5 a1 a2 a3 a4 t oelqv t oehqz ssclk sswe ssce ssads dq addr ssoe t khkl t klkh t khkh t s t h t s t s t h fig. 4 ssram write timing t khg wx t t h t s d ( a1) d ( a2 ) d ( a3 ) d ( a4 ) d ( a5 ) a1 a2 a3 a4 a5 s h ssclk sswe ssce ssads dq addr ssoe t h t khkl t klkh t khkh t s t h t h t s t h
8 white electronic designs corporation ?(508) 366-5151 ?www.whiteedc.com wed9lc6416v january 2001 sdram ac characteristics (v cc = 3.3v -5% / +10% unless otherwise noted; 0 c t a 70 c, commercial; -40 c t a 85 c, industrial) symbol 125mhz 100mhz 83mhz parameter min max min max min max units clock cycle time (1) cl = 3 t cc 8 1000 10 1000 12 1000 ns cl = 2 t cc 10 1000 12 1000 15 1000 clock to valid output delay (1,2) t sac 678ns output data hold time (2) t oh 33 3ns clock high pulse width (3) t ch 33 3ns clock low pulse width (3) t cl 33 3ns input setup time (3) t ss 22 2ns input hold time (3) t sh 11 1ns clk to output low-z (2) t slz 22 2ns clk to output high-z t shz 778ns row active to row active delay (4) t rrd 20 20 24 ns ras\ to cas\ delay (4) t rcd 20 20 24 ns row precharge time (4) t rp 20 20 24 ns row active time (4) t ras 50 10,000 50 10,000 60 10,000 ns row cycle time - operation (4) t rc 70 80 90 ns row cycle time - auto refresh (4,8) t rfc 70 80 90 ns last data in to new column address delay (5) t cdl 1 1 1 clk last data in to row precharge (5) t rdl 1 1 1 clk last data in to burst stop (5) t bdl 1 1 1 clk column address to column address delay (6) t ccd 1.5 1.5 1.5 clk number of valid output data (7) 2 2 2 12 1 ea notes: 1. parameters depend on programmed cas latency. 2. if clock rise time is longer than 1ns (t rise /2 -0.5)ns should be added to the parameter. 3. assumed input rise and fall time = 1ns. if t rise of t fal l are longer than 1ns. [(t rise = t fall )/2] - 1ns should be added to the parameter. 4. the minimum number of clock cycles required is detemined by dividing the minimum time required by the clock cycle time and th en rounding up to the next higher integer. 5. minimum delay is required to complete write. 6. all devices allow every cycle column address changes. 7. in case of row precharge interrupt, auto precharge and read burst stop. 8. a new command may be given t rfc after self-refresh exit.
9 white electronic designs corporation ?(508) 366-5151 ?www.whiteedc.com wed9lc6416v january 20001 mode register set l l l l x op code auto refresh (cbr) l l l h x x x precharge single bank l l h l x ba l 2 precharge all banks l l h l x x h bank activate l l h h x ba row address 2 write l h l l x ba l 2 write with auto precharge l h l l x ba h 2 read l h l l x ba l 2 read with auto precharge l h l h x ba h 2 burst termination l h h l x x x 3 no operation l h h h x x x device deselect h x x x x x x data write/output disable x x x x l x x 4 data mask/output disable x x x x h x x 4 notes: 1. all of the sdram operations are defined by states of sdce\, sdwe\, sdras\, sdcas\, and bwe 0-3 at the positive rising edge of the clock. 2. bank select (ba), if a 12 (ba 0 ) and a 13 (ba 1 ) select between different banks. 3. during a burst write cycle there is a zero clock delay, for a burst read cycle the delay is equal to the cas latency. 4. the bwe has two functions for the data dq read and write operations. during a read cycle, when bwe goes high at a clock timin g the data outputs are disabled and become high impedance after a two clock delay. bwe also provides a data mask function for write cycles. when it activates, the write operation at the clock is prohibited (zero clock latency). function sdce sdras sdcas sdwe bwe a 12 , a 13 sda 10 notes a 11-0 sdram command truth table clock frequency and latency parameters - 125mhz sdram (unit = number of clock) frequency cas t rc t ras t rp t rrd t rcd t ccd t cdl t rdl 70ns 50ns 20ns 20ns 20ns 10ns 10ns 10ns 125mhz (8.0ns) 3 9 6 3 2 3 1 1 1 100mhz (10.0ns) 3 7 5 2 2 2 1 1 1 83mhz (12.0ns) 2 6 4 2 2 2 1 1 1 latency clock frequency and latency parameters - 100mhz sdram (unit = number of clock) frequency cas t rc t ras t rp t rrd t rcd t ccd t cdl t rdl 70ns 50ns 20ns 20ns 20ns 10ns 10ns 10ns 100mhz (12.0ns) 3 7 5 2 2 2 1 1 1 83mhz (12.0ns) 2 6 5 2 2 2 1 1 1 latency -10 -12 parameter symbol min max min max units refresh period (1,2) t ref ?4 64 ms notes: 1. 4096 cycles 2. any time that the refresh period has been exceeded, a minimum of two auto (cbr) refresh commands must be given to "wake-up" t he device. refresh cycle parameters
10 white electronic designs corporation ?(508) 366-5151 ?www.whiteedc.com wed9lc6416v january 2001 mode register set table a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 11 10 9 8 7 6 5 4 3 2 1 0 reserved* wb op mode cas latency bt burst length address bus mode register (mx) m2 m1 m0 m3 = 0 m3 = 1 000 1 1 001 2 2 010 4 4 011 8 8 1 0 0 reserved reserved 1 0 1 reserved reserved 1 1 0 reserved reserved 1 1 1 full page reserved burst length m3 burst type 0 sequential 1 interleaved m2 m1 m0 cas latency 0 0 0 reserved 0 0 1 reserved 010 2 011 3 1 0 0 reserved 1 0 1 reserved 1 1 0 reserved 1 1 1 reserved m8 m7 m6-m0 operating mode 0 0 defined standard operation --- --- --- all other states reserved m9 write burst mode 0 programmed burst length 1 single location access *should program m11, m10 = "0, 0" to ensure compatibility with future devices.
11 white electronic designs corporation ?(508) 366-5151 ?www.whiteedc.com wed9lc6416v january 20001 l l l l op code mode register set set the mode register 1 l l l h x x auto or self refresh start auto 1 l l h l x x precharge no operation l l h h ba row address bank activate activate the specified bank and row idle l h l l ba column write w/o precharge illegal 2 l h l h ba column read w/o precharge illegal 1 l h h l x x burst termination no operation 1 l h h h x x no operation no operation h x x x x x device deselect no operation l l l l op code mode register set illegal l l l h x x auto or self refresh illegal l l h l x x precharge precharge 3 l l h h ba row address bank activate illegal 1 row active l h l l ba column write start write; determine if auto precharge 4,5 l h l h ba column read start read; determine if auto precharge 4,5 l h h l x x burst termination no operation l h h h x x no operation no operation h x x x x x device deselect no operation l l l l op code mode register set illegal l l l h x x auto or self refresh illegal l l h l x x precharge terminate burst; start the precharge l l h h ba row address bank activate illegal 2 read l h l l ba column write terminate burst; start the write cycle 5,6 l h l h ba column read terminate burst; start a new read cycle 5,6 l h h l x x burst termination terminate the burst l h h h x x no operation continue the burst h x x x x x device deselect continue the burst l l l l op code mode register set illegal l l l h x x auto or self refresh illegal l l h l x x precharge terminate burst; start the precharge l l h h ba row address bank activate illegal 2 write l h l l ba column write terminate burst; start a new write cycle 5,6 l h l h ba column read terminate burst; start the read cycle 5,6 l h h l x x burst termination terminate the burst l h h h x x no operation continue the burst h x x x x x device deselect continue the burst l l l l op code mode register set illegal l l l h x x auto or self refresh illegal l l h l x x precharge illegal 2 read with l l h h ba row address bank activate illegal 2 auto precharge l h l l ba column write illegal l h l h ba column read illegal l h h l x x burst termination illegal l h h h x x no operation continue the burst h x x x x x device deselect continue the burst sdram current state truth table current state command action notes sdce sdras sdcas sdwe (ba) a 11- a 0 description a 12 & a 13
12 white electronic designs corporation ?(508) 366-5151 ?www.whiteedc.com wed9lc6416v january 2001 l l l l op code mode register set illegal l l l h x x auto or self refresh illegal l l h l x x precharge illegal 2 write with l l h h ba row address bank activate illegal 2 auto precharge l h l l ba column write illegal l h l h ba column read illegal l h h l x x burst termination illegal l h h h x x no operation continue the burst h x x x x x device deselect continue the burst l l l l op code mode register set illegal l l l h x x auto or self refresh illegal l l h l x x precharge no operation; bank(s) idle after t rp l l h h ba row address bank activate illegal 2 precharging l h l l ba column write w/o precharge illegal 2 l h l h ba column read w/o precharge illegal 20 l h h l x x burst termination no operation; bank(s) idle after t rp l h h h x x no operation no operation; bank(s) idle after t rp h x x x x x device deselect no operation; bank(s) idle after t rp l l l l op code mode register set illegal l l l h x x auto or self refresh illegal l l h l x x precharge illegal 2 l l h h ba row address bank activate illegal 2 row activating l h l l ba column write illegal 2 l h l h ba column read illegal 2 l h h l x x burst termination no operation; row active after t rcd l h h h x x no operation no operation; row active after t rcd h x x x x x device deselect no operation; row active after t rcd l l l l op code mode register set illegal l l l h x x auto orself refresh illegal l l h l x x precharge illegal 2 l l h h ba row address bank activate illegal 2 write recovering l h l l ba column write start write; determine if auto precharge 6 l h l h ba column read start read; determine if auto precharge 6 l h h l x x burst termination no operation; row active after t dpl l h h h x x no operation no operation; row active after t dpl h x x x x x device deselect no operation; row active after t dpl l l l l op code mode register set illegal l l l h x x auto orself refresh illegal l l h l x x precharge illegal 2 write recovering l l h h ba row address bank activate illegal 2 with auto l h l l ba column write illegal 2,6 precharge l h l h ba column read illegal 2,6 l h h l x x burst termination no operation; precharge after t dpl l h h h x x no operation no operation; precharge after t dpl h x x x x x device deselect no operation; precharge after t dpl sdram current state truth table (cont.) current state command action notes sdce sdras sdcas sdwe (ba) a 11- a 0 description a 12 & a 13
13 white electronic designs corporation ?(508) 366-5151 ?www.whiteedc.com wed9lc6416v january 20001 notes: 1. both banks must be idle otherwise it is an illegal action. 2. the current state refers only refers to one of the banks, if ba selects this bank then the action is illegal. if ba selects t he bank not being referenced by the current state then the action may be legal depending on the state of that bank. 3. the minimum and maximum active time (t ras ) must be satisfied. 4. the ras to cas delay (t rcd ) must occur before the command is given. 5. address sda 10 is used to determine if the auto precharge function is activated. 6. the command must satisfy any bus contention, bus turn around, and/or write recovery requirements. the command is illegal if the minimum bank to bank delay time (t rrd ) is not satisfied. l l l l op code mode register set illegal l l l h x x auto or self refresh illegal l l h l x x precharge illegal l l h h ba row address bank activate illegal refreshing l h l l ba column write illegal l h l h ba column read illegal l h h l x x burst termination no operation; idle after t rc l h h h x x no operation no operation; idle after t rc h x x x x x device deselect no operation; idle after t rc l l l l op code mode register set illegal l l l h x x auto or self refresh illegal l l h l x x precharge illegal mode register l l h h ba row address bank activate illegal accessing l h l l ba column write illegal l h l h ba column read illegal l h h l x x burst termination illegal l h h h x x no operation no operation; idle after two clock cycles h x x x x x device deselect no operation; idle after two clock cycles current state command action notes sdce sdras sdcas sdwe (ba) a 11- a 0 description sdram current state truth table (cont.) a 12 & a 13
14 white electronic designs corporation ?(508) 366-5151 ?www.whiteedc.com wed9lc6416v january 2001 fig. 5 sdram single bit read-write-read cycle (same page) @ cas latency = 3, burst length = 1 sdras sdcas addr ba bwe t ss t sh sda 10 sdclk sdce cb cc rb ca ra t sh dq row active precharge read write read row active db qc sdwe 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 t ss t sh t rcd t rp t ras t rcd t ss t sh t ss bs bs bs bs bs note 3 note 3 note 4 rb note 3 note 2, 3 note 2, 3 note 2 note 4 note 2, 3 ra bs qa t sh t ss t oh t sac t slz t ss t sh t ss t sh t rac t ss t sh t ccd t ch t cl t cc don?t care
15 white electronic designs corporation ?(508) 366-5151 ?www.whiteedc.com wed9lc6416v january 20001 fig. 6 sdram power up sequence key raa mode register set row active (a-bank) auto refresh auto refresh precharge (all banks) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 t rp raa high-z t rfc t rfc high level is necessary don?t care sdras sdcas addr ba bwe sda 10 sdclk sdce dq sdwe
16 white electronic designs corporation ?(508) 366-5151 ?www.whiteedc.com wed9lc6416v january 2001 fig. 7 sdram read & write cycle at same bank @ burst length = 4 rb cb0 ca0 ra cl = 2 dq row active (a-bank) write (a-bank) precharge (a-bank) precharge (a-bank) read (a-bank) row active (a-bank) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 t rcd t rc rb note 1 ra qa0 t shz t shz t rdl t rdl t rac t rac qa1 qa2 qa3 db0 db1 db2 db3 cl = 3 qa0 qa1 qa2 qa3 db0 db1 db2 db3 t sac t sac t oh t oh note 3 note 4 note 4 note 3 don ? t care sdras sdcas addr ba bwe sda 10 sdclk sdce sdwe notes: 1. minimum row cycle times are required to complete internal dram operation. 2. row precharge can interrupt burst on any cycle. (cas latency - 1) number of valid output data is available after row precharg e. last valid output will be hi-z (t shz ) after the clock. 3. access time from row active command. t cc *(t rcd + cas latency - 1) + t sac . 4. output will be hi-z after the end of burst. (1, 2, 4, 8 & full page bit burst)
17 white electronic designs corporation ?(508) 366-5151 ?www.whiteedc.com wed9lc6416v january 20001 fig. 8 sdram page read & write cycle at same bank @ burst length = 4 cc0 cd0 ca0 ra cl = 2 write (a-bank) write (a-bank) read (a-bank) precharge (a-bank) read (a-bank) row active (a-bank) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 t rcd ra qa0 t rdl t cdl qa1 qb0 qb1 qb2 dc0 dc1 dd0 dd1 cl = 3 qa0 qa1 qb0 qb1 dc0 dc1 dd0 dd1 don ? t care cb0 note 2 note 3 note 1 dq sdras sdcas addr ba bwe sda 10 sdclk sdce sdwe notes: 1. to write data before burst read ends. bwe should be asserted three cycle prior to write command to avoid bus contention. 2. row precharge will interrupt writing. last data input, t rdl before row precharge will be written. 3. bwe should mask invalid input data on precharge command cycle when asserting precharge before end of burst. input data after row precharge cycle will be masked internally.
18 white electronic designs corporation ?(508) 366-5151 ?www.whiteedc.com wed9lc6416v january 2001 fig. 9 sdram page read cycle at different bank @ burst length = 4 cac cbd cae rbb caa raa cl = 2 read (a-bank) read (a-bank) read (b-bank) row active (b-bank) read (b-bank) precharge (a-bank) read (a-bank) row active (a-bank) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 raa qaa2 qaa3 qbb0 qbb1 qbb2 qbb3 qac0 qac1 qbd0 qbd1 qae0 qae1 cl = 3 qaa2 qaa3 qaa0 qaa1 qaa0 qaa1 qbb0 qbb1 qbb3 qbb2 qac0 qac1 qbd0 qbd1 qae0 qae1 don ? t care cbb note 2 note 1 rbb dq sdras sdcas addr ba bwe sda 10 sdclk sdce sdwe notes: 1. sdce can be dont care when sdras, sdcas and sdwe are high at the clock going high edge. 2. to interrupt a burst read by row precharge, both the read and the precharge banks must be the same.
19 white electronic designs corporation ?(508) 366-5151 ?www.whiteedc.com wed9lc6416v january 20001 fig. 10 sdram page write cycle at different bank @ burst length = 4 cac cbd rbb caa raa write (a-bank) write (b-bank) row active (b-bank) write (b-bank) precharge (both banks) write (a-bank) row active (a-bank) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 raa daa3 dbb0 dbb1 dbb2 dbb3 dac0 dac1 dbd0 dbd1 daa1 daa0 daa2 don ? t care cbb note 2 note 1 rbb t rdl t cdl sdras sdcas addr ba bwe sda 10 sdclk sdce dq sdwe notes: 1. to interrupt burst write by row precharge, bwe should be asserted to mask invalid input data. 2. to interrupt a burst read by row precharge, both the read and the precharge banks must be the same.
20 white electronic designs corporation ?(508) 366-5151 ?www.whiteedc.com wed9lc6416v january 2001 fig. 11 sdram read & write cycle at different bank @ burst length = 4 rac cac caa rbb raa cl = 2 read (a-bank) row active (a-bank) read (a-bank) write (b-bank) precharge (a-bank) row active (b-bank) row active (a-bank) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 raa qaa3 dbb0 dbb1 dbb2 dbb3 qac0 qac1 qaa1 qaa0 qaa2 don ? t care cbb note 1 rac rbb t cdl qac2 cl = 3 dq qaa3 dbb0 dbb1 dbb2 dbb3 qac0 qac1 qaa1 qaa0 qaa2 sdras sdcas addr ba bwe sda 10 sdclk sdce sdwe notes: 1. t cdl should be met to complete write.
21 white electronic designs corporation ?(508) 366-5151 ?www.whiteedc.com wed9lc6416v january 20001 fig. 12 sdram read & write cycle with auto precharge @ burst length = 4 cb ca rb ra cl = 2 auto precharge start point (b-bank) auto precharge start point (a-bank) write with auto precharge (b-bank) read with auto precharge (a-bank) row active (b-bank) row active (a-bank) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 ra qa3 db0 db1 db2 db3 qa1 qa0 qa2 don ? t care rb cl = 3 dq qa3 db0 db1 db2 db3 qa1 qa0 qa2 sdras sdcas addr ba bwe sda 10 sdclk sdce sdwe notes: 1. t cdl should be controlled to meet minimum t ras before internal precharge start. (in the case of burst length = 1 & 2 and brsw mode)
22 white electronic designs corporation ?(508) 366-5151 ?www.whiteedc.com wed9lc6416v january 2001 fig. 13 sdram read interrupted by precharge command & read burst stop @ burst length = full page cab caa raa cl = 2 precharge (a-bank) read (a-bank) burst stop read (a-bank) row active (a-bank) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 don ? t care raa qaa0 qaa1 qaa2 qaa3 qaa4 qab1 qab0 qab3 qab2 qab5 qab4 cl = 3 dq qaa0 qaa1 qaa2 qaa3 qaa4 qab1 qab0 qab3 qab2 qab5 qab4 note 2 1 1 2 2 sdras sdcas addr ba bwe sda 10 sdclk sdce sdwe notes: 1. at full page mode, burst is end at the end of burst. so auto precharge is possible. 2. about the valid dqs after burst stop, it is the same as the case of sdras interrupt. both cases are illustrated in the above timing diagram. see the label 1, 2 on each of them. but at burst write, burst stop and sdras interrupt should be compared carefully. refer to the timing diagram of full page write burst stop cycle. 3. burst stop is valid at every burst length.
23 white electronic designs corporation ?(508) 366-5151 ?www.whiteedc.com wed9lc6416v january 20001 fig. 14 sdram write interrupted by precharge command & write burst stop @ burst length = full page cab caa raa dq precharge (a-bank) write (a-bank) burst stop write (a-bank) row active (a-bank) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 don ? t care raa daa0 daa1 daa2 daa3 daa4 dab1 dab0 dab3 dab2 dab5 dab4 note 2 t rdl t bdl sdras sdcas addr ba bwe sda 10 sdclk sdce sdwe notes: 1. at full page mode, burst is end at the end of burst. so auto precharge is possible. 2. data-in at the cycle of interrupted by precharge can not be written into the corresponding memory cell. it is defined by ac p arameter of t rdl . bwe at write interrupt by precharge command is needed to prevent invalid write. bwe should mask invalid input data on precharge command cycle when asserting precharge before end of burst. input data after ro w precharge cycle will be masked internally. 3. burst stop is valid at every burst length.
24 white electronic designs corporation ?(508) 366-5151 ?www.whiteedc.com wed9lc6416v january 2001 fig. 15 sdram burst read single bit write cycle @ burst length = 2 cbc cad rbb caa raa cl = 2 row active (a-bank) read (a-bank) row active (b-bank) write with auto precharge (b-bank) precharge (both banks) write (a-bank) read with auto precharge (a-bank) row active (a-bank) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 raa qab0 qab1 dbc0 qad0 qad1 daa0 don ? t care cab note 2 rbb rac rac cl = 3 dq qab0 qab1 dbc0 qad0 qad1 daa0 sdras sdcas addr ba bwe sda 10 sdclk sdce sdwe notes: 1. brsw modes enabled by setting a9 high at mrs (mode register set). at the brsw mode, the burst length at write is fixed to 1 regardless of programmed burst length. 2. when brsw write command with auto precharge is executed, keep it in mind that t ras should not be violated. auto precharge is executed at the burst-end cycle, so in the case of brsw write command, the next cycle starts the precharge.
25 white electronic designs corporation ?(508) 366-5151 ?www.whiteedc.com wed9lc6416v january 20001 fig. 16 sdram mode register set cycle ra key dq new command new command auto refresh mrs 012 3456 012345 678910 don't care t rfc hi-z hi-z note 2 note 1 note 3 sdras sdcas addr bwe sdclk sdce sdwe *both banks precharge should be completed before mode register set cycle and auto refresh cycle. notes: mode register set cycle 1. sdce, sdras, sdcas & sdwe activation at the same clock cycle with address key will set internal mode register. 2. minimum 2 clock cycles should be met before new sdras activation. 3. please refer to mode register set table. sdram auto refresh cycle high
26 white electronic designs corporation ?(508) 366-5151 ?www.whiteedc.com wed9lc6416v january 2001 package description: 153 lead bga (17 x 9 ball array) jedec mo-163 part number ssram access sdram access wed9lc6416v2012bc 200mhz 125mhz wed9lc6416v2010bc 200mhz 100mhz wed9lc6416v1612bc 166mhz 125mhz wed9lc6416v1610bc 166mhz 100mhz wed9lc6416v1512bc 150mhz 125mhz wed9lc6416v1510bc 150mhz 100mhz wed9lc6416v1312bc 133mhz 125mhz wed9lc6416v1310bc 133mhz 100mhz ordering information all linear dimensions are millimeters and parenthetically in inches 3.50 (0.138) max 1.27 (0.050) typ a b c d e f g h j k l m n p r t u 14.00 (0.551) bsc pin 1 index 22.00 (0.866) bsc commercial (0 c t a 70 c) industrial (-40 c t a 85 c) part number ssram access sdram access wed9lc6416v2012bi 200mhz 125mhz WED9LC6416V2010BI 200mhz 100mhz wed9lc6416v1612bi 166mhz 125mhz wed9lc6416v1610bi 166mhz 100mhz wed9lc6416v1512bi 150mhz 125mhz wed9lc6416v1510bi 150mhz 100mhz wed9lc6416v1312bi 133mhz 125mhz wed9lc6416v1310bi 133mhz 100mhz
27 white electronic designs corporation ?(508) 366-5151 ?www.whiteedc.com wed9lc6416v january 20001 fig. 17 interfacing the texas instruments tms320c6x with the wed9lc6416v (128kx32 ssram/4mx32 sdram) a 0 a 1 a 2 a 3 a 4 a 5 a 6 a 7 a 8 a 9 a 10 a 11 a 12 a 13 a 14 a 15 a 16 sswe\ ssce\ ssoe\ ssadc\ ssclk bwe 0 \ bwe 1 \ bwe 2 \ bwe 3 \ sda 10 sdce\ sdras\ sdcas\ sdwe\ sdclk sswe\ ce 2 \ ssoe\ ssads\ ssclk be 0 \ be 1 \ be 2 \ be 3 \ sda 10 ce 0 \ sdras\ sdcas\ sdwe\ sdclk dq 0-7 dq 8-15 dq 16-23 dq 24-31 address bus ea 2-21 data bus ed 0-31 texas instruments tms320c6x dsp wed9lc6416v 128k x 32 ssram 4m x 32 sdram ssram control sdram control shared controls ea 2 ea 3

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